This invention relates to programmable logic array integrated circuits, and more particularly to programmable logic array integrated circuits with improved arrangements of the programmable logic elements and improved interconnections between those elements.
Programmable logic arrays are known in which substantial numbers of relatively elementary individual programmable logic elements are provided in a two-dimensional array. The array also includes a grid of intersecting signal conductors for conducting logic signals to, from, and between the programmable logic elements. Such programmable logic arrays are shown, for example, in Carter U.S. Pat. Nos. 4,642,487, 4,706,216, and 4,758,985, and in Freeman U.S. Pat. No. 4,870,302.
As integrated circuit fabrication techniques progress, it becomes possible to put more and more programmable logic elements on a chip. As the number of elements increases, it becomes important to improve the techniques used to interconnect them. For example, it is important to provide enough interconnection pathways between the programmable logic elements so that the capabilities of those elements can be fully utilized and so that complex logic functions (requiring concatenation of programmable logic elements) can be performed, without providing so many such pathways that there is a wasteful excess of this type of resource. Similarly, as the number of programmable elements increases, the complexity of the logic which can be performed also increases. But this in turn tends to increase the complexity of the task of programming the circuit unless additional logical structure is included in the circuit to help correspondingly structure the programming task.
In view of the foregoing, it is an object of this invention to provide improved techniques for organizing and interconnecting the programmable logic elements in programmable logic array integrated circuits.
It is another object of this invention to provide improved programmable logic array integrated circuits.